Output buffers found in integrated circuits provide an interface for driving external loads, both capacitive and inductive. External capacitive loads typically consist of the bonding wire, the pin, conductors on the printed circuit board, and the input capacitances of the gates to which an output buffer is coupled. The inductive load usually comprises the series parasitic inductances of the power supply and ground lines supplying the output buffer which in turn are coupled to the external power and ground rails on the printed circuit board.
With traditional output buffers (i.e. an inverter chain), output transistor sizing is constrained by DC operating characteristics. This leads to several problems: unacceptably high current peaks which occur with the simultaneous switching of many output buffers; inductive power supply noise which results in large voltage drops, and electromagnetic interference due to high output edge switching rates.
Inductive switching noise appears as an undesired undershoot or overshoot in the internal power supply or ground voltage rails, as the buffer supplies current to or sinks current from an external load.
The resulting noise voltage is harmful in many ways. Firstly, non-switching circuits which share the same power and/or ground rails are subject to the switching noise of active circuits, potentially causing spurious transitions at the inputs of the non-switching circuits. Secondly, switching speed is degraded since the noise narrows the gap between the power supply and ground voltage levels. Inductive switching noise is exacerbated when there is simultaneous switching of two or more circuits.
Prior art solutions to these problems include reducing the signal swing, but at the cost of abandoning TTL compatibility, along with the added penalty of having to provide an extra power supply voltage. A simple approach is to slow down the turn-on time of the output switching transistor, but at the cost of having a transition time that is load-dependent and increasing the propagation delay.
A circuit is required which provides a load independent slew rate controlled output signal. The circuit should be simple in design so that a minimum amount of silicon is needed to implement the circuit.